How to measure FPGA clock speed?

Short version: you can’t “ask” the FPGA what GHz it runs at like a CPU — you either know it from the design/tools or you measure a clock at a pin / with logic.

Here are the practical ways people do it.

1. Check the known clock sources (no hardware needed)

Usually easiest and often all you need.

1. Look at your board docs / schematic

• There is almost always a crystal/oscillator labeled something like “100 MHz”, “50 MHz”, “12 MHz”, etc.
• That signal goes to an FPGA pin and is your base clock.

2. Check your clock generator / PLL settings

• Xilinx: Clocking Wizard / PLL / MMCM IP → you choose input freq + multiply/divide → tool tells you output freq.
• Intel/Altera: ALTPLL / Clock control IP → same idea.

3. Look in your constraints & timing reports

• Xilinx (XDC): lines like

create_clock -name sys_clk -period 10.000 [get_ports SYS_CLK_P]  ; # 100 MHz

• Timing summary will say:

“Clock: sys_clk (period = 10.000 ns, freq = 100.0 MHz)”

If you just want to know “what frequency did I design for?”, the above is enough.

2. Measure at a pin with an oscilloscope or logic analyzer

If you want to physically confirm the clock:

Step 1 – Route the clock (or divided clock) to an output pin

Often you don’t want to drive the raw high-speed clock out; instead you divide it by 2/4/8 and measure that.

Example in Verilog:

module clk_test(
    input  wire clk_in,     // your internal clock
    output reg  clk_out_div // divided clock to a pin
);

always @(posedge clk_in) begin
    clk_out_div <= ~clk_out_div; // toggle => f_out = f_in / 2
end

endmodule

Now constrain clk_out_div to a physical pin in your .xdc/.qsf and set an IO standard (e.g. LVCMOS33).

Step 2 – Measure it

• Attach a scope probe or logic analyzer to that pin and GND.
• Measure the period or use a frequency measurement function.
• If you divided by 2 (like above), then:

𝑓FPGA clock=2×𝑓measured

Tips:

• Use a reasonably low division if your scope bandwidth is limited (e.g. divide 100 MHz down to 10 MHz).
• Don’t put a big load on the pin (no LEDs directly without resistor, short wires, etc.).

3. Measure internally using a counter (no external instruments)

If you have two clocks (one reference, one unknown) you can measure the unknown using a counter.

Idea

• Use a known reference clock clk_ref (e.g. 50 MHz) to define a time window.
• Count how many edges of the unknown clock clk_unknown occur in that window.

Conceptual Verilog (simplified):

module freq_meter(
    input  wire clk_ref,       // known, e.g. 50 MHz
    input  wire clk_unknown,   // clock to measure
    input  wire reset_n,
    output reg [31:0] count_latched
);

reg [31:0] ref_cnt = 0;
reg [31:0] unk_cnt = 0;

// Count unknown clock edges
always @(posedge clk_unknown or negedge reset_n) begin
    if (!reset_n)
        unk_cnt <= 0;
    else
        unk_cnt <= unk_cnt + 1;
end

// Use reference clock to define gate time
always @(posedge clk_ref or negedge reset_n) begin
    if (!reset_n) begin
        ref_cnt      <= 0;
        count_latched <= 0;
    end else begin
        ref_cnt <= ref_cnt + 1;
        // Example: gate time = 1 ms = (50_000 cycles @ 50 MHz)
        if (ref_cnt == 50_000 - 1) begin
            ref_cnt       <= 0;
            count_latched <= unk_cnt; // samples count every 1 ms
            unk_cnt       <= 0;
        end
    end
end

endmodule

Then you can:

• Read count_latched via UART, JTAG, ILA, GPIO, etc.
• Since the gate time is 1 ms, the frequency ≈ count_latched × 1000 Hz.

You can adjust the gate time for more resolution.

4. Use on-chip logic analyzer / debug tools

If you’re using vendor tools:

• Xilinx/AMD: Integrated Logic Analyzer (ILA).
• Intel: SignalTap.

You can:

1. Tap an internal clock (or a divided version).
2. Capture a small run.
3. Inspect edges in the waveform view and measure period.

This is more indirect, but handy if you can’t easily bring signals to pins.

5. “Clock speed” vs “max frequency” (important distinction)

Two different concepts:

1. Actual clock frequency

Set by your oscillator + PLL settings (what we just measured).

2. Maximum safe frequency (Fmax)

• Determined by timing analysis: how fast the combinational paths can run.
• Tools give you “Slack” and a max frequency for each clock domain.
• If you run the clock faster than this, the design may fail.

So:

• Use oscillator/PLL & measurement to know “What frequency am I running at?”.
• Use timing reports to know “How fast can I safely run this design?”.